In the field of microelectronic circuit design, a particular circuit may be represented by a netlist, which is a data file or other data compilation specifying the descriptions and interconnections of the electrical elements in the circuit. Within a netlist, the electrical elements and their interconnections are labeled, or named, according to naming conventions particular to the specific format of the netlist.
Typical computer-aided-engineering (CAE) tools employed in the design of microelectronics circuits may use one or more specific netlist formats to enable the automated processing of the circuit during the design phases. Each specific netlist format, such as Verilog, EDIF, or VHDL, employs a particular naming convention which may be incompatible with another specific netlist format. As a result, it is generally not possible to use the name of an netlist element in one specific netlist format when translating that netlist into another specific netlist format.
The names in a netlist constrained by these naming conventions may include names of logic cell types, logic cells instances, input, output, and bidirectional ports, and interconnections (nets) among instances of logic cells. Although the naming conventions of these various netlist formats are known in the art, the need exists for a method of generating translations of names in specific netlist formats so as to realize format-independent names.